Method for Electroplating and Contact Projection Arrangement

ABSTRACT

A method for electroplating is provided in which a copper layer is patterned using a resist. A barrier layer lies below the copper layer and is used to supply the electroplating current in regions without the copper layer. The method makes it possible to produce high-quality soldering bumps.

PRIORITY CLAIM

The present application is a continuation of International PatentApplication Serial No. PCT/EP2004/052999, filed Nov. 17, 2004, andclaims the benefit of priority of German Patent Application No. 103 55953.1, filed Nov. 29, 2003, both of which are hereby incorporated byreference.

BACKGROUND

1. Technical Field

The invention relates to a method of electroplating. In particular, theinvention relates to a method of electroplating for a contactprojection.

2. Background Information

Copper is a very inexpensive material having a high electricalconductivity. Consequently, a copper layer is well suited to supplyingthe current during electroplating. Therefore, copper is a material thatis often used as a material for the auxiliary layer.

The mask layer is e.g. a resist layer which is patterned by means of aphotolithographic method. For example, a contact projection made of asolderable material, which is also referred to in the jargon as“soldering bump”, is electrodeposited in the mask opening. Tin alloys,for example, in particular tin-lead alloys or more environmentallycompatible tin-silver alloys, are used as soldering material.

The basic layer, the auxiliary layer and the mask layer are preferablyapplied over the whole area. The basic layer and the auxiliary layer areapplied by sputtering, for example.

During electroplating, the substrate to be coated is dipped into anelectrolyte bath and connected as cathode. On account of theelectrochemical processes brought about by the voltage, material—theso-called cations—deposits from the electrolyte on the substrate.Optional additives in the electrolyte bath enable specific properties ofthe deposited layer to be influenced in a targeted manner.

BRIEF SUMMARY

The invention relates to a method for electroplating in which thefollowing steps are performed:

application of an electrically conductive basic layer to a substrate,

application of an auxiliary layer having better electrical conductivityin comparison with the basic layer after the application of the basiclayer,

application of a mask layer after the application of the auxiliarylayer, e.g. a resist layer,

production of a mask with at least one mask opening from the mask layer,electroplating of a layer in the mask opening.

The substrate is for example a semiconductor substrate with onemetallization layer or with a plurality of metallization layers. Siliconsemiconductor substrates are often used. The metallization contains forexample more than eighty atomic percent of aluminum or more than eightyatomic percent of copper.

The electrically conductive basic layer is e.g. an adhesion promotinglayer for increasing the mechanical adhesion and/or a diffusion barrierlayer for preventing diffusion. By way of example, titanium nitridelayers are used as copper barrier layers. In connection with a contactprojection, the basic layer and auxiliary layer are also referred to inthe jargon as “under bump metallization” (UBM).

It is an object of the invention to specify an improved method forelectroplating which can be used in particular to produce contactprojections having good mechanical and electrical properties. Moreover,the intention is to specify a contact projection having good mechanicaland electrical properties.

The object referring to the method is achieved by means of a methodhaving the method steps specified in patent claim 1. Developments arespecified in the subclaims.

In the case of the method according to the invention, in addition to themethod steps mentioned in the introduction, the following steps areperformed:

patterning of the auxiliary layer using the mask or resist mask, thebasic layer not being patterned or not being completely patternedaccording to the resist mask, and

electroplating of a layer in the resist opening after the patterning ofthe auxiliary layer.

The invention is based on the consideration that the auxiliary layer ison the one hand required for rapid electroplating with homogeneous layergrowth. On the other hand, residues of the auxiliary layer below thedeposited layer are often disturbing, for example with regard tocorrosion or with regard to the formation of specific interfaces.Therefore, the auxiliary layer is removed in the case of the methodaccording to the invention by means of a mask beneath a resist opening,said mask being required anyway for the definition of the electroplatingzone. In this case, however, the basic layer is not concomitantlyremoved beneath the resist opening. The basic layer is likewiseelectrically conductive and thus suitable for current transport duringelectroplating.

The lower current-carrying capacity of the basic layer is not of verygreat consequence since the auxiliary layer is present as far as themask opening and is used for current transport. In the comparativelysmall electroplating zone in comparison with the substrate surface, thecurrent-carrying capacity is increased as the thickness of the depositedlayer increases. By way of example, the electroplating zone has an areaof less than 40 percent or less than 20 percent of the substratesurface.

New layer sequences can be electrodeposited by the method according tothe invention because restrictions are circumvented by the auxiliarylayer. It is thus possible to produce in particular contact projectionshaving good electrical properties, in particular having high resistanceto electromigration, and having a high mechanical adhesion. The contactprojections are suitable in particular for the flip-chip technique orfor the chip high-speed mounting technique, in which a multiplicity ofconnections are produced simultaneously by soldering, by microwelding orby bonding using conductive adhesive or using conductive varnish.

In one development, the following steps are performed:

electroplating with a current density in an initial phase, and

electroplating with a higher current density in comparison with thecurrent density during the initial phase in a main phase following theinitial phase.

This procedure takes account of the lower current-carrying capacity ofthe basic layer because in the initial phase with a comparatively lowcurrent density a layer having a greater electrical conductivity thanthe basic layer is deposited at the bottom of the openings penetratingthrough the auxiliary layer. Only when this layer has for example aconductivity corresponding to the thickness of the auxiliary layer (e.g.greater layer thickness), that is to say the auxiliary layer has been“repaired” again with another material, is the current density increasedto the high value in order to effect electroplating rapidly.

In one development, the current density in the initial phase is lessthan 50 percent of the current density in the main phase. The initialphase is longer than 5 seconds and shorter than 5 minutes. In onerefinement, the transition from the initial phase to the main phasetakes place with a uniform rise in current over time. In anotherrefinement, the current density is increased multiply in accordance witha stepped sequence, current densities that remain the same in themeantime being used. A superposition of these current density functionswith current pulses is also carried out.

In one development, the current density in the main phase is greaterthan 0.2 ampere per square decimeter and less than 10 ampere per squaredecimeter (ASD), e.g. 0.5 A/cm-2. The current density values mentionedrelate to the opened resist area on the wafer surface.

In a next development, the following steps are performed:

application of an insulating layer prior to the application of the basiclayer, and

patterning of the insulating layer with production of a contact openingprior to the application of the basic layer.

In the case of a contact projection, the insulating layer is for examplea passivation layer which contains for example a silicon oxide layerand/or a silicon nitride layer. The contact opening lies below the maskopening for the electroplating. If the mask opening is chosen to besomewhat wider than the contact opening, then the removal of theresidues of the already prepatterned auxiliary layer and of the parts ofthe basic layer which lie outside the arrangement to be produced isfacilitated since the insulating layer is used as an etching stop layer.

In a next development, the basic layer is a barrier layer against copperdiffusion. The auxiliary layer contains copper or comprises copper andis thus particularly well suited to feeding the electroplating current.However, copper is also a material which is particularly corrosive inthe presence of moisture, since mixed oxides arise particularly readily,which are also referred to as verdigris. Said mixed oxides considerablyreduce the adhesion of the layers in the arrangement to be produced. Thecurrent conductivity during operation of the integrated circuitarrangement would thus also be considerably reduced. Since the auxiliarylayer is completely removed, in particular in the region in which thelayer is electrodeposited or in which the layers are electrodeposited,these disadvantages are not manifested, particularly if the arrangementis also moreover free of copper. In particular, there is also no needfor any additional measures for encapsulating copper-containing layersand thus protecting them from moisture.

In another development, the following steps are performed:

electroplating of a base layer, and

electroplating of a covering layer after the electroplating of the baselayer, the base layer comprising a different material than the coveringlayer.

Consequently, a layer stack is deposited which permits combinationeffects to be obtained, for example the formation of specific compoundsduring a subsequent reflow process or the improvement of mechanicalproperties of the arrangement to be produced.

In one development, the material of the base layer has a melting pointof greater than 500 degrees Celsius and is thus resistant to soldering.The material of the covering layer has a melting point of less than 400degrees Celsius and is thus solderable. The invention additionallyrelates to a contact projection arrangement, which is also referred toas a soldering bump. The soldering bump contains in the following orderwith increasing distance from a substrate of an integrated circuit:

an electrically conductive interconnect for lateral current transport ora connection plate, which is also referred to as a connection pad andserves for vertical current transport, that is to say in a directionexactly opposite to a direction of the normal to a substrate main area,

an electrically conductive basic layer, in particular an adhesionpromoting and barrier layer,

adjoining the basic layer a copper-free base layer made of a materialhaving a melting point of greater than 500 degrees Celsius, and

preferably adjoining the base layer an electrically conductive soldermaterial layer having a melting point of less than 400 degrees Celsius.

The contact projection arrangement according to the invention can beproduced particularly well by means of the method according to theinvention or one of its developments. In particular, a copper-freecontact projection arrangement can be produced using a copper auxiliarylayer during electroplating.

In one development, the base layer contains at least 60 atomic percentof nickel. By way of example, the base layer comprises nickel,nickel-phosphorus or nickel-chromium. Nickel forms a ternary compoundwith the solder material, e.g. the tin-silver in a boundary layer, thethickness of the boundary layer being limited by self-regulation duringthe formation of the ternary compounds. Additional measures for definingthe thickness of the boundary layer are therefore not necessary. Theboundary layer forms an effective barrier against electromigration and,on the other hand, increases the electrical resistance only to a stillacceptable extent. The ternary compounds, for example as intermetallicphases, build up a complicated space lattice.

In one development, the interconnect or the connection plate comprisesat least 80 atomic percent of aluminum. As an alternative, however,copper is used as a constituent, with its proportion being more than 50atomic percent.

In one development, the basic layer forms a diffusion barrier forcopper, so that the copper of the auxiliary layer does not penetrateinto the interconnect. In one development, the basic layer comprisestitanium-tungsten or contains titanium-tungsten, the proportion oftitanium preferably being less than 20 atomic percent. The barrier andadhesion properties of this layer are particularly good. However, othermaterials are also suitable, such as titanium, tantalum, titaniumnitride or tantalum nitride, and layer combinations of these materialsare furthermore also possible, e.g. a layer sequence made of a titaniumlayer, a titanium-tungsten layer and a titanium layer.

If the basic layer adjoins the interconnect, then no further layers aresituated between the basic layer and the interconnect, so that thecontact projection arrangement has a simple construction. In particular,no copper-containing layer that would have to be protected againstcorrosion is situated between the interconnect and the basic layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is explained below with reference to the accompanyingfigures, in which:

FIGS. 1A to 1B show production stages during the production of asoldering bump.

FIG. 2 shows a plan view of the soldering bump after the deposition of anickel base and prior to the deposition of solder material.

DETAILED DESCRIPTION

FIGS. 1A to 1B show production stages during the production of asoldering bump 10. The method begins proceeding from a substrate 12,which contains for example a plurality of metallization layers (notillustrated) and a main body made of silicon. The metallization layersin each case contain a multiplicity of interconnects and vias which areinsulated by an intralayer dielectric within a metallization layer andby an interlayer dielectric between adjacent metallization layers. Amultiplicity of semiconductor components, e.g. field effect transistorsof a memory circuit or of a processor, are formed on the main body madeof silicon.

As illustrated in FIG. 1A, an upper aluminum layer 14 is applied to thesubstrate 12 and patterned using a photolithographic method, aconnection pad 16 being produced. The aluminum layer 14 and also theconnection pad 16 have for example a thickness in the range from 500nanometers to 2 micrometers, 500 nanometers in the exemplary embodiment.The connection pad 16 has for example a rectangular or square basicarea. In the exemplary embodiment, the basic area is octagonal, thedistance between two mutually opposite sides of the hexagon beingapproximately 80 micrometers. The aluminum layer 14 contains only smalladditions of less than 5 atomic percent, for example 0.5 atomic percent,of silicon, and if appropriate a copper addition, in particular 1 atomicpercent.

After the patterning of the aluminum layer 14, a passivation layer 18 isdeposited. The passivation layer 18 has for example a layer thickness inthe range from 500 nanometers to 1 micrometer, 500 nanometers in theexemplary embodiment. The passivation layer 18 contains for example anoxide layer and an overlying nitride layer. With the aid of aphotolithographic method, a multiplicity of cutouts are introduced intothe passivation layer 18 for soldering bumps, one cutout 20 of which isillustrated in FIG. 1A. The cutout 20 is for example likewise octagonal,but has a smaller diameter than the connection pad 16. In the exemplaryembodiment, the diameter of the cutout 20 is approximately 60micrometers.

After the production of the cutout 20, a titanium-tungsten barrier layer22 is applied over the whole area, the layer thickness of said barrierlayer lying e.g. in the range from 100 nanometers to 200 nanometers. Inthe exemplary embodiment, the barrier layer 22 has a layer thickness of100 nanometers. The barrier layer 22 contains for example more than 80atomic percent of tungsten. In the exemplary embodiment, the proportionof tungsten is 90 atomic percent and the proportion of titanium is 10atomic percent. The barrier layer 22 is applied by sputtering, forexample.

After the application of the barrier layer 22, a copper layer 24 made ofpure copper, e.g. with a proportion of copper of greater than 98 atomicpercent, is applied over the whole area. The thickness of the copperlayer 24 lies for example in the range from 80 nanometers to 150nanometers. In the exemplary embodiment, the copper layer 24 has athickness of 100 nanometers. By way of example, the copper layer 24 isapplied by sputtering.

As is further illustrated in FIG. 1A, a resist layer 26, e.g. with alayer thickness of 100 micrometers, is subsequently applied to thecopper layer 24. The resist layer 26 is exposed and developed, a cutout28 arising above the cutout 20. The cutout 28 is likewise octagonal, buthas a somewhat larger diameter than the cutout 20. The diameter of thecutout 28 is 80 micrometers in the exemplary embodiment. The cutouts 20and 28 lie concentrically with respect to one another.

As is further illustrated by a dashed line 30 in FIG. 1A, after thedevelopment of the resist layer 26, the copper is removed at the bottomof the cutout 28 by patterning of the copper layer 24 according to themask formed by the resist layer 26. By way of example, wet-chemicaletching is effected, undercuts 32 of the copper layer 32 beingnoncritical, as will be explained in greater detail below. In anotherexemplary embodiment, the cutouts are kept small on account of anoptimization of the etching and amount to less than 2 micrometers.

As shown in FIG. 1B, a nickel base 50 is subsequently electrodeposited,the copper layer 24 critically serving for carrying current outside thecutout 28. Only at the bottom of the cutout 28 does the barrier layer 20critically serve for feeding current, in particular at the start ofelectroplating. By way of example, in accordance with the electroplatingmethod specified above, firstly electroplating is effected onlycomparatively slowly with a low current density. Once the nickel base 50has a layer thickness like the copper layer 24, that is to say a layerthickness of 100 nanometers in the exemplary embodiment, a changeover ismade gradually or in steps to a higher current density for fasterelectroplating. The nickel base 50 is deposited for example with a layerthickness of 2 micrometers to 5 micrometers. In the exemplaryembodiment, the layer thickness of the nickel base is 3 micrometers.

During the deposition of the nickel base 50, the undercuts 32 or thesecavities do not cause a disturbance because possible depositions in thisregion do not adversely affect the functionality of the contactprojection.

As is further shown in FIG. 1B, solder material 52 is subsequentlyelectrodeposited, a high current density being used directly at thebeginning. In the exemplary embodiment, the solder material is atin-silver solder deposited with a layer thickness in the range of 50 to120 micrometers. In the exemplary embodiment, the solder material 52 hasa layer thickness of 90 micrometers.

The electrodepositions of the nickel base 50 and of the solderingmaterial 52 are conformal. An edge 54 of the cutout 20 is mapped as edge56 on the nickel base 50 and as edge 58 on the solder material 52.

FIG. 1C shows that after the deposition of the solder material 52, theresist layer 26 is removed again, so that the soldering bump 10 isuncovered. The residues of the copper layer 24 are subsequently removedfrom the barrier layer 22 by wet-chemical or dry-chemical means.Afterward but if appropriate by means of the same etching method, thebarrier layer 22 is removed in regions which are not covered by thenickel base 50. A barrier layer region 22 a arises between the nickelbase 50 and the connection pad 16. The barrier layer region 22a projectsbeyond the cutout 20 and bears on the passivation layer 18 in thevicinity of the cutout 22 a, for example in a vicinity of less than 15micrometers. Further away from the cutout 20, by contrast, the barrierlayer 22 was removed.

With regard to the removal of the copper layer 24 and of the barrierlayer 22, the smallest possible layer thicknesses are chosen for thecopper layer 24 and for the barrier layer 22 but without impairing theiractual current feeding function and barrier function, respectively, toan excessively great extent.

The soldering bump 10 is subsequently heated in a reflow stepmomentarily to a temperature of 400 degrees Celsius, for example, thesolder material 52 being reshaped in spherical fashion. A thin boundarylayer containing, inter alia, the ternary alloy tin-nickel-silver formsat the boundary 70 between nickel base and solder material.

FIG. 2 shows a plan view of the soldering bump 10 after the depositionof the nickel base 50 and prior to the deposition of the solder material52. The plan view was originally photographed, the resist layer 26previously having been removed. The octagonal connection pad 16adjoining for example an interconnect 80 of a rewiring plane is readilydiscernible. The titanium-tungsten barrier layer 22 is uncovered in theregion of the undercuts 32, which have a width B1 of up to 10micrometers in the circumferential direction.

The nickel base 50 is delimited by the cutout 28 and has a diameter D of80 micrometers. The edge 56 of the nickel base 50 is also readilydiscernible.

It holds true in summary that the auxiliary layer, in particular thecopper layer, is selectively removed in the contact windows, inparticular by wet-chemical or galvanic etching-back, which is alsoreferred to as deplating. During galvanic etching-back, the substrate isconnected as an anode from which material is removed. The worked-backregion is subsequently built again by an electrochemical deposition,e.g. a nickel deposition. Consequently, copper-free interfaces, inparticular, are present below the soldering bumps. The followingtechnical effects result:

-   -   severe disturbing metallic phase formations, e.g. of copper and        tin, no longer occur, and    -   after resist removal, it is thus possible, under certain        circumstances, to remove the UBM (Under Bump Metallization) in a        single etching step. This etching is optimized for the removal        of the barrier, e.g. titanium or titanium-tungsten. The        auxiliary layer and the barrier layer are preferably removed in        the same etching chamber, in particular by means of the same        etching chemical or etching chemical composition.    -   the undercut of the soldering bump is minimized.    -   for removing the auxiliary layer in the contact windows, it is        also possible to use the same electroplating installation as in        the case of deposition within the mask opening, without the        substrate being taken from the installation in the meantime,    -   a plating, for example a nickel plating, directly on to the        barrier layer becomes possible.

A preferred field of application is radio frequency circuits andhousings with more than 100 connections which are mounted in accordancewith the flip-chip technique. Prior to the electrochemical deposition ofsolder balls or soldering bumps, a metal barrier, e.g. a titanium layeror a titanium-tungsten layer, and an auxiliary layer, e.g. a copperlayer, are applied as a whole-area electrode on the wafer. These twolayers may be regarded as UBM (Under Bump Metallization) and are appliedfor example by magnetron sputtering or electron beam evaporation.

The barrier layer prevents metallic interdiffusion from the soldermaterial into the interconnects on the wafer. The auxiliary layer servesas a current-carrying contact-making layer for the electroplatingprocess.

After the lithography, opened resist contact windows are ready forfilling with bump metallizations. The electroplating process begins witha wetting or prewetting step for uniformly wetting the contacts with theelectrolyte. The first metal layer that is intended to be grown isnickel, for example, e.g. a so-called stud having a thickness of 2 to 5micrometers or having a thickness in the range of 5 micrometers to 100micrometers, in particular having a thickness of greater than 40micrometers. The solder metallization is subsequently deposited withthicknesses of up to 50 micrometers or up to 150 micrometers.

After resist removal, the barrier layer and the auxiliary layer must beremoved again. Wet-chemical methods are employed here. In the course ofwet etching, no undesirable undercuts and no corrosion arise as a resultof the procedure explained, so that the solder ball still adheres wellto the wafer surface.

Particularly in the case of auxiliary layers made of copper, theformation of severe intermetallic phases of copper with tin and theassociated complete dissolution of copper in the tin-silver solder andalso the formation of pores at the interface to the barrier are avoided.A stripping away of the bumps and a failure of the system areeffectively prevented.

It is therefore intended that the foregoing detailed description beregarded as illustrative rather than limiting, and that it be understoodthat it is the following claims, including all equivalents, that areintended to define the spirit and scope of this invention.

1-14. (canceled)
 15. A method for electroplating comprising: applying anelectrically conductive base layer to a substrate; applying an auxiliarylayer having a better electrical conductivity in comparison with thebase layer after applying the base layer; applying a mask layer afterapplying the auxiliary layer; producing a mask with at least one maskopening from the mask layer; patterning the auxiliary layer using themask, wherein the base layer is not patterned or not completelypatterned according to the mask; and electroplating at least one layerin the mask opening after the patterning of the auxiliary layer.
 16. Themethod as claimed in claim 15, further comprising: electroplating with acurrent density in an initial phase; and electroplating with a highercurrent density in comparison with the current density during theinitial phase in a main phase following the initial phase.
 17. Themethod as claimed in claim 16, wherein the current density in theinitial phase has a value of less than 50 percent of the current densityin the main phase, and wherein the initial phase is longer than 5seconds and shorter than 5 minutes, and wherein the current density inthe main phase is greater than 0.2 ampere per square decimeter and lessthan 10 amperes per square decimeter.
 18. The method as claimed in claim17, further comprising: applying an insulating layer prior to applyingthe base layer, patterning the insulating layer by producing a contactopening prior to the application of the base layer; and applying a partof the base layer in the contact opening.
 19. The method as claimed inclaim 18, wherein applying the base layer comprises applying a barrierlayer against copper diffusion, and wherein applying the auxiliary layercomprises applying a layer comprising copper.
 20. The method as claimedin claim 19, further comprising: electroplating a base layer; andelectroplating a covering layer after the electroplating of the baselayer, and wherein the base layer comprises a different material fromthe covering layer.
 21. The method as claimed in claim 20, wherein thebase layer has a melting point of greater than 500 degrees Celsius, andwherein the material of the covering layer has a melting point of lessthan 400 degrees Celsius.
 22. The method as claimed in claim 21, whereinpatterning of the auxiliary layer comprises galvanic patterning of theauxiliary layer.
 23. A contact projection arrangement comprising: atleast one of an electrically conductive interconnect or a connectionplate; an electrically conductive base layer; a copper-free base layeradjoining the basic layer, wherein the copper-free base layer comprisesa material having a melting point of greater than 500 degrees Celsius;and an electrically conductive solder material layer having a meltingpoint of less than 400 degrees Celsius.
 24. The contact projectionarrangement as claimed in claim 23, wherein the base layer comprises atleast one of nickel or nickel-phosphorus, or at least 60 atomic percentof nickel.
 25. The contact projection arrangement as claimed in claim23, further comprising a boundary layer of binary or multiphasecompounds, and wherein the boundary layer is present at the boundarybetween the base layer and the solder material layer.
 26. The contactprojection arrangement as claimed in claim 23, wherein at least one ofthe interconnect or the connection plate contains at least 80 atomicpercent of aluminum, or wherein at least one of the interconnect or theconnection plate contains more than 50 atomic percent of copper, andwherein the solder material layer includes a tin alloy, and wherein thebasic layer comprises a diffusion barrier for copper, and wherein thebasic layer comprises titanium-tungsten, wherein the proportion oftitanium is less than 20 atomic percent, and wherein the basic layercomprises a layer stack made of a plurality of component layers, thelayer stack containing at least one of the following layers: a titaniumlayer, a tantalum layer, a titanium nitride layer, a tantalum nitridelayer, a tungsten layer, a titanium-tungsten layer or a titaniumtungsten nitride layer.
 27. The contact projection arrangement asclaimed in claim 23, wherein the basic layer adjoins the interconnect orthe connection plate, and wherein the base layer adjoins the soldermaterial layer.
 28. The contact projection arrangement as claimed inclaim 23, further comprising an electrically insulating layer with acutout in which at least part of the basic layer and part of the baselayer are arranged.
 29. The method as claimed in claim 16, wherein theinitial phase is longer than 5 seconds or shorter than 5 minutes. 30.The method as claimed in claim 16, wherein the current density in theinitial phase has a value of less than 50 percent of the current densityin the main phase, and wherein the initial phase is at least one oflonger than 5 seconds and shorter than 5 minutes, and wherein thecurrent density in the main phase is at least one of greater than 0.2ampere per square decimeter or less than 10 amperes per squaredecimeter.
 31. The method as claimed in claim 22 wherein the galvanicpatterning comprises galvanic patterning in the same installation as theelectroplating of the layer in the mask opening.
 32. The method asclaimed in claim 23, wherein the boundary layer comprises a ternarycompound.
 33. The method as claimed in claim 16, wherein the tin alloycomprises at least one of a tin-silver alloy, a tin-lead alloy, atin-silver-copper alloy, or a tin-silver-bismuth alloy.
 34. The contactprojection arrangement as claimed in claim 23, wherein the basic layeradjoins the interconnect or the connection plate, or wherein the baselayer adjoins the solder material layer.
 35. A semiconductor devicecomprising: a substrate; an electrically conductive base layer appliedto the substrate; an auxiliary layer having a better electricalconductivity in comparison with the base layer after applying the baselayer; a mask layer applied after applying the auxiliary layer; a maskincluding at least one mask opening, wherein the at least one maskopening is produced from the mask layer, wherein the auxiliary layer ispatterned using the mask, wherein the base layer is not patterned or notcompletely patterned according to the mask; and at least one layer inthe mask opening, wherein the at least one layer is electroplated afterthe patterning of the auxiliary layer.
 36. The semiconductor device asclaimed in claim 35, wherein the at least one layer is electroplatedwith a current density in an initial phase, and electroplated with ahigher current density in comparison with the current density during theinitial phase in a main phase following the initial phase.
 37. Thesemiconductor device as claimed in claim 36, wherein the current densityin the initial phase has a value of less than 50 percent of the currentdensity in the main phase, and wherein the initial phase is longer than5 seconds and shorter than 5 minutes, and wherein the current density inthe main phase is greater than 0.2 ampere per square decimeter and lessthan 10 amperes per square decimeter.
 38. The semiconductor device asclaimed in claim 17, further comprising: an insulating layer appliedprior to applying the base layer, a contact opening produced bypatterning the insulating layer prior to the application of the baselayer; and a part of the base layer, wherein the part of the base layeris applied in the contact opening.